H-bridge drive system 2-way pulse width modulation circuit driving a motor control signal to control the positive and negative work in both directions, and two signals must have a certain time interval to avoid excessive damage to the drive current drive components.  Flexibility to make the application requirements for the system, PWM controller should have the following functions:

 3 way independent PWM outputs, each output two drive signals, cycle, programmable dead time, corresponding to 10MHz system clock, the cycle is 1μs-6.5536ms;

Streamline the address line, saving the external pin and address of the resource consumption;

 SCM provides two-way data interface 8/16bits, built-in address / data latch.

PWM structure planning

 The introduction of top-down (Top_Down) forward design, the structure of the chip division, customization is the entire design specification of the most important part, reasonable structure design will determine the success or failure of the whole design [1] [2].

 PWM output signal of the cycle, pulse width, the dead time and other parameters can be loaded to achieve an internal register, write the data points PWM chip data word and control word in two parts.  By internal control logic module to control word information processing, and decoding of information generated within the internal channels of the chip select signal register.  Data word through the internal data bus in each channel PWM module features information and data transfer.

 Each chip module to read and write through the combination of the internal chip select enabled completion of data exchange.  Peripheral controller chip and dual-mode data exchange interfaces (8/16bits), can be selected by external pin DataWidth to matching.

 The core chip is completely independent from the three modules and the same channel.  Channel will be completed within the external data interface to read and write logic (RWLogic) transferred to the internal data bus data transceiver work.  PWM cycle generation module is based on the information written to the cycle, the output PWM cycle control signal.

 PWM output from the channel state machine, PWM channel receives the information data, data validation, data will be qualified to start in the right conditions, the state machine, and in a different state of complete PWM output.  Failure data will be ignored.

 Address / data latch is based on common 74LS373 logic function, write a complete alternative to the L 74LS373 to achieve.

 According to the general construction approaches, the final overall structure of the chip shown in Figure 1.

PWM circuit design

 From the opening can be seen in Figure 1, PWM modules mainly by the chip select decoding, control logic, channel four modules, some of the features of each briefly described below.

 Module chip select decoding module and the chip select address signal Addr Csb signal generated by the internal logic of the combination of the sub-module chip-select signal.