The author is engaged in system design, when changes in some performance analog devices but can not update the back end of the digital baseband processor to adjust the time, such as filters because of long working hours due to the impact of temperature drift characteristics, this when programmable analog devices can replace part of the analog front-end fixed, and then in real time on the FPGA dynamically reconfigurable module operation, and ultimately achieve optimized system performance.

 Programmable Analog

 Programmable Analog emerging in recent years a new type of integrated circuits.  It belongs to analog integrated circuits, that circuit's input, output or internal state are continuously changing with time and amplitude of the analog signal has not been quantified; the same time, such device is field programmable, and can be changed by the user through the device configuration to obtain the required circuit function. To support the programmability, programmable analog device needs to programmable analog unit (CAB) and programmable interconnection network (PIN) as the core, with the configuration data memory, input units, output units or input \ output units, etc. constitute [1] (see Figure 1).

Figure 1 Block diagram of programmable analog devices

 Most programmable analog devices on a single +5 V supply voltage, rated power consumption is 100mW order of magnitude.  As a result of special measures, the input and output linear range is usually up to near full supply voltage range; closed-loop bandwidth has reached hundreds of kHz to tens MHz; frequency distortion, common-mode rejection ratio, the internal noise and other indicators has also been reached in the level of precision operational amplifiers.

 Although lower than the accuracy of analog signal processing digital signal processing, but still many important applications to meet the requirements of accuracy, while the smaller circuits required, the cost is lower.  While taking advantage of its programmability, you can achieve accurate automatic tuning and automatic gain control, communication systems significantly improve anti-jamming capability.

Implementation of phase detector

。 TRAC (fully re-configurable analog circuit) is the UK's FAS series field programmable analog devices in general.  It provides a departure from the signal processing problem, solve a variety of common signal processing problem. Reference to the computing device unit and the analog computer to be expanded within the device are available for each programmable analog unit to add, subtract, take the negative, logarithmic, the number opposed, integral, differential expression of 8 kinds of functions, so only the selected the type of operation and give the necessary parameters, we can easily complete the design of the relevant units, there is no need to consider the internal structure of the circuit elements and other details.  Taken between the internal unit from left to right in the form of a fixed connection, all cells of the input \ output leads to the device pins are, and allow use of the units are available "through" and "off" function or use Add the "short route" to modify this basic connection [1] (see Figure 2).

 Schematic diagram of the device Figure 2 TRAC

 The author is engaged in cognitive radio hardware platform design, a strong signal from the background due to the need to identify the environment to extract weak signals and thus the device can be constituted by TRAC phase sensitive detector, and as part of the amplifier latch.  To achieve this goal, as the circuit work as narrow-band filter to remove most do not want to be a strong signal to allow only weak signals under test.

 Figure 3 shows the basic block diagram of the phase detector.  Switch the input signal and reference signal with the same frequency and phase.  Shown in the output from the switch is expected to get a full-wave rectified signal, and after low-pass filter, the signal can be received and the exchange potential DC voltage proportional to output.  In practice, the input signal may be very small, therefore also need to join the preamp level to support the accurate detection. Because usually requires a continuous change within a certain frequency of reference signal, while measuring the corresponding DC output.  Similarly, if the need to detect a single frequency, the reference signal must be measured the same input signal frequency.  Since the phase phase detector is also sensitive, so when the two signal phase will also get the maximum output voltage.

 Figure 3 Block diagram of phase detector

 Phase detector and low pass filters like the need to use two devices to achieve the TRAC.。 The external components are essential for the amplifiers and filters, so the components must satisfy the condition a reasonable value.

Implementation of Programmable ADC

 Cognitive radio receiver front-end with its high-performance analog - digital converter (ADC) and analog requirements are higher, and FPGA in baseband digital signal processing, but also an urgent need for dynamic re-configuration. 。 To meet the above requirements, you can first consider the use of programmable analog device to achieve the ADC, the following are two concrete implementations.

 FIPSOC mixed-signal system on a chip

 SIDSA's FIPSOC mixed-signal system on a chip is the rapid development of analog and digital integrated application the ideal tool. FIPSOC FIPSOC chip includes embedded enhanced 8051 microprocessor, field programmable gate array (FPGA) and a set of signal conditioning and data acquisition for applications can be flexibly configurable analog modules.  And separation of the analog, digital, FPGA program compared with FIPSOC mixed-signal system on a chip, can shorten product design cycles of 30 ~ 40%.

 Programmable analog, digital units and 8051 single-chip system includes a simulation unit, conversion unit, programmable digital unit, the 8051 kernel and the series compatible with all devices have the memory distribution, which contains a 4-way conversion unit DAC (resolution can be configured to 8-10), the use of successive approximation algorithm can be used to these DAC sampling rates up to 800KHz ADC (see Figure 4).

 Figure 4 a block diagram of the data conversion module

 Data conversion module contains four 8-bit successive approximation register (SAR), which can be joint work within the DAC to get analog / digital conversion.

 Each channel has an independent SAR, it receives the results of successive approximation, and drive the corresponding DAC, the conversion of each channel can be carried out independently.  When the conversion module is programmed to 9 or 10-bit ADC conversion, the formation of the corresponding SAR Group: ADC 9 when, SAR1 and SAR2 as a group, SAR3 and SAR4 as a group; 10-bit ADC, all four form a group of SAR  At this time, a group of SAR 1 to 2 of their work cycle, the end of the conversion, SAR will be hosting its content in the input / output register, and enable the interrupt module.  In continuous conversion mode, will start the next conversion.  In the conversion process, programmable logic module can be independently released the convert command, which will convert this and the next brings error.  In continuous conversion mode, which will lead to a fatal error, because errors can be passed and will be unpredictable results.

 The control section is a standard 8051 microprocessor.  Compound, the 8051 first programmable cell nuclear configuration, the configuration can be used as a generic after the microprocessor.  In order to better support the dynamic reconfiguration feature FIPSOC has its instructions and functional unit made some improvements.