"In the past ten years, Altera has been continuously and discusses the future of the embedded application customers. We found their needs are focused on four aspects: to improve system performance and reduce the power consumption of the system, reduce the area of the circuit board and lower the cost of the overall system. With the power consumption of the FPGA device of falling, many clients plan in the next generation of embedded design inside FPGA use to replace the old expensive and time-consuming design." Altera company product and the enterprise market vice President Vince Hu said.

Recently, Altera publish its based on ARM of SoC FPGA series products, in a single chip integrated 28 nm Cyclone V and Arria V FPGA structure, dual-core 800 MHz ARM of the Cortex-A9 MPCore processor, the ECC (ECC) protect the memory controller, peripherals and broadband Internet, etc. These SoC FPGA inherited ARM rich software development tools, debugger, operating system, middleware and application procedures auxiliary system function. The user can use the SoC FPGA Altera development process, quickly establishing customizable based on ARM of the system, which can reduce the various industries of the embedded system, power consumption and cost board area, while increasing performance.

The Cyclone V and Altera Arria V SoC FPGA processor with NEON media processing engine, single/double precision floating-point unit, L1 and L2 cache, ECC memory controller protection, ECC protection high-speed temporary storage, as well as various common peripherals. The processor system performance to the peak of 4000 DMIPS, and power consumption less than 1.8 W. The processor system and FPGA framework independent power supply, can in any order configuration and start.
Work after get up, can according to need to shut off the FPGA part, in order to reduce the power consumption of the system. Through the big throughput data access realize ARM Cortex-A9 MPCore processor system and FPGA interconnection of peak bandwidth more than 125-Gbps, and keep good data continuity. Because the processor and FPGA not using IO pathways between external substantially reduces the power system.

Cyclone V and Arria V SoC FPGA based on low power consumption 28-nm process (28 LP). These series respectively in 5-with work Gbps and 10 Gbps-the embedded transceiver. FPGA framework including precision adjustable DSP module, and three ECC memory controller protection. Altera's Cyclone V SoC FPGA has 110 K logic unit (LE), system power consumption and low cost, the device performance level is very suitable for mass application, including the next generation of chip industry drive, senior assistant driving and video monitoring, etc. For medium application, Arria V SoC FPGA in cost and performance to equilibrium, total power consumption are the lowest. Device has 460 K LE, suitable to meet the performance requirements of high application, including, remote rf, LTE base station and multi-functional printers, etc.

SoC FPGA virtual target a development environment

In the mature Synopsys development solution of virtual prototyping, based on the virtual targets are based on SoC FPGA PC in Altera SoC FPGA development circuit boards function simulation. The virtual targets and SoC FPGA circuit board binary and registers compatible, the function is equivalent to ensure that the developers with minimum of the workload in the virtual targets will be developed on software transplanted to the actual printed circuit board. Embedded software engineer using the virtual targets, use familiar with tools to development and application software, maximum limit to use the existing code, the use of the target control of the unprecedented and target visual function, and to further improve the efficiency.

Vince Hu said: "for embedded project development application software usually need to take a lot of time and engineering resources. The adoption of our SoC FPGA, we help engineer the virtual targets quickly began to their software development, for example: engineers in the previous debug stage takes about three to four weeks of development time, reduced to less than 1 week now, this big increases in the design efficiency and make products can be more rapid listed."